Field of the Invention
The invention relates to a differential, complementary amplifier having two complementary amplifier paths, each including a p-channel transistor and an n-channel transistor connected in series. Amplifiers of this type serve for amplifying differential analog or digital input signals. They have a wide range of application and are suitable, in particular, for amplifying high-frequency signals with data rates up to the Gbit/s range.
U.S. Pat. No. 4,937,476 discloses a differential amplifier having two amplifier paths that are arranged in parallel and that each have a pair of CMOS transistors. A third pair of CMOS transistors controls the current supply for the two amplifier paths and sets the operating point thereof. To that end, the output of the drain terminalsxe2x80x94connected to one anotherxe2x80x94of the first amplifier path is connected to the gate terminals of the third CMS transistor pair. The known amplifier makes an output voltage available at the output of the second amplifier path for a differential voltage present at the gate terminals of the two amplifier paths.
U.S. Pat. No. 4,958,133 describes a differential, complementary amplifier having CMOS amplifier paths arranged in parallel. An improved negative feedback is described that provides a high degree of common-mode rejection and a high voltage gain for differential signals.
In the differential amplifiers disclosed in the two documents mentioned, one path of the amplifier always functions solely to stabilize the operating-point and the other path of the amplifier serves as the actual amplifier. As a result, the gain is limited in the case of a relatively large current consumption. Moreover, the abovementioned amplifier circuits in each case have only a xe2x80x9csingle endedxe2x80x9d output. This prevents the use of a simple series circuit with a second differential amplifier stage.
A further differential, complementary amplifier having two amplifier paths is described in U.S. Pat. No. 6,028,467.
It is accordingly an object of the invention to provide a differential, complementary amplifier which overcomes the above-mentioned disadvantages of the prior art apparatus of this general type.
In particular, it is an object of the invention to provide a differential, complementary amplifier that provides a relatively high gain in conjunction with high bandwidth and low current consumption and that also enables a simple interconnection of a plurality of amplifier stages.
With the foregoing and other objects in view there is provided, in accordance with the invention, a differential, complementary amplifier including: a first complementary MOSFET amplifier path including a p-channel transistor and an n-channel transistor connected in series; a second complementary MOSFET amplifier path including a p-channel transistor and an n-channel transistor connected in series; a first load resistor and a second load resistor; and a node. The second amplifier path is operated in an opposite direction relative to the first amplifier path. The output of the first amplifier path and the output of the second amplifier path form a differential output. The first load resistor connects the output of the first amplifier path to the node. The second load resistor connects the output of the second amplifier path to the node. The operating point of the first amplifier path and the second amplifier path is set by a voltage present at the node.
In accordance with an added feature of the invention, the first amplifier path and the second amplifier path are driven by half of the operating voltage.
In accordance with an additional feature of the invention, the first amplifier path and the second amplifier path have a bandwidth that is variable by varying the first load resistor and the second load resistor.
In accordance with another feature of the invention, there is provided, at least a first FET control transistor and a second FET control transistor for controlling a current supplied to the first amplifier path and to the second amplifier path. The first FET control transistor has a gate terminal connected to the node. The second FET control transistor has a gate terminal connected to the node. The operating point of the first amplifier path and the second amplifier path is set by setting a voltage on the gate of the first FET control transistor and a voltage on the gate of the second FET control transistor.
In accordance with another added feature of the invention, the first FET control transistor is a p-channel control transistor; the second FET control transistor is an n-channel control transistor; and the first FET control transistor and the second FET control transistor are connected in series and form a complementary MOSFET transistor pair.
In accordance with another additional feature of the invention, there is provided, a terminal for receiving an operating voltage; and a ground terminal. The p-channel control transistor has a source terminal connected to the terminal for receiving the operating voltage. The n-channel control transistor has a source terminal connected to the ground terminal. The p-channel control transistor has a drain terminal. The n-channel control transistor has a drain terminal. The first amplifier path and the second amplifier path are configured between the drain terminal of the p-channel control transistor and the drain terminal of the n-channel control transistor.
In accordance with a further feature of the invention, the p-channel transistor of the first amplifier path has a source terminal; the p-channel transistor of the second amplifier path has a source terminal; the n-channel transistor of the first amplifier path has a source terminal; the n-channel transistor of the second amplifier path has a source terminal; the drain terminal of the p-channel control transistor is connected to the source terminal of the p-channel transistor of the first amplifier path and to the source terminal of the p-channel transistor of the second amplifier path; and the drain terminal of the n-channel control transistor is connected to the source terminal of the n-channel transistor of the first amplifier path and to the source terminal of the n-channel transistor of the second amplifier path.
In accordance with a further added feature of the invention, the first FET control transistor and the second FET control transistor are operated in a triode region.
In accordance with a further additional feature of the invention, the p-channel transistor of the first amplifier path and the p-channel transistor of the second amplifier path are identically constructed; and the n-channel transistor of the first amplifier path and the n-channel transistor of the second amplifier path are identically constructed.
In accordance with yet an added feature of the invention, there is provided a capacitor coupled to the node.
In accordance with yet an additional feature of the invention, there is provided, at least a first FET control transistor and a second FET control transistor for controlling a current supplied to the first amplifier path and to the second amplifier path. The first FET control transistor has a gate terminal, and the second FET control transistor has a gate terminal. A first low-pass filter connects the node to the gate terminal of the first control transistor, and a second low-pass filter connects the node to the gate terminal of the second control transistor.
In accordance with yet another feature of the invention, there is provided, at least a first FET control transistor and a second FET control transistor for controlling a current supplied to the first amplifier path and to the second amplifier path; a first current mirror circuit including a MOSFET transistor having an input connected to the node; and a second current mirror circuit including a MOSFET transistor having an input connected to the node. The first control transistor has a source terminal, and the second control transistor has a source terminal. The MOSFET transistor of the first current mirror circuit has an output connected to the source terminal of the first control transistor. The MOSFET transistor of the second current mirror circuit has an output connected to the source terminal of the second control transistor. The first current mirror circuit is assigned to the first control transistor. The second current mirror circuit is assigned to the second control transistor.
In accordance with an added feature of the invention, the first control transistor and the second control transistor are operated in a pinch-off region.
In accordance with an additional feature of the invention, there is provided, a negative feedback device for the first amplifier path and for the second amplifier path.
In accordance with another feature of the invention, the first amplifier path has source terminals; the second amplifier path has source terminals; the negative feedback device includes a first resistor connected to one of the source terminals of the first amplifier path and to one of the source terminals of the second amplifier path; and the negative feedback device includes a second resistor connected to another one of the source terminals of the first amplifier path and to another one of the source terminals of the second amplifier path.
In accordance with a further feature of the invention, there is provided, a terminal for receiving an operating voltage; a ground terminal; and two control transistors of identical size having gate terminals connected to the node and source terminals connected to the terminal for receiving the operating voltage, each one of the two control transistors having a drain terminal connected to a respective one of the first amplifier path and the second amplifier path. Two further control transistors of identical size have gate terminals connected to the node and source terminals connected to the ground terminal. Each one of the two further control transistors have a drain terminal connected to a respective one of the first amplifier path and the second amplifier path. One of the control transistors and one of the further control transistors are associated with the first amplifier path. Another one of the control transistors and another one of the further control transistors are associated with the second amplifier path. The first amplifier path and the second amplifier path define two paths. At least one resistor connects the first amplifier path to the second amplifier path at a location between the two control transistors and the two paths. At least one further resistor connects the first amplifier path to the second amplifier path at a location between the two further control transistors and the two paths.
In accordance with a further added feature of the invention, there is provided, a capacitor connected in parallel with the first resistor of the feedback device; and a capacitor connected in parallel with the second resistor of the feedback device.
In accordance with a further additional feature of the invention, the first amplifier path and the second amplifier path are configured for amplifying high-frequency signals.
In other words, in a differential amplifier having two amplifier paths, the second amplifier path is operated in the opposite direction relative to the first amplifier path. Outputs of the two amplifier paths form a differential output and are in each case connected to one another via a load resistor at a node. The operating point of the two amplifier paths is set by the voltage present at that node. According to the invention, the differential load is in this case divided into two individual resistors and the voltage present between the individual resistors serves for setting the operating point of the amplifier paths. The bandwidth and the gain can be influenced by varying the resistances of the load resistors.
Because of the fact that the amplifier paths operate relative to one another, voltage differences present at the respective amplifier paths are amplified with a doubled amplitude. Accordingly, a high gain is manifested. Setting the operating point of the two amplifier paths by way of the voltage present at the node between the two load resistors of the amplifier paths enables an accurate setting of the operating point since the voltage at the node has almost no AC components. On account of the symmetrical circuit dimensioning, a voltage amounting to half of the operating voltage (Vdd/2) is established in this case. Furthermore, the operating-point setting is xe2x80x9cself-biasedxe2x80x9d because of the feedback that takes place.
According to the invention, the amplifier is provided with a differential output, i.e. the difference between the voltages at the output nodes of the amplifier can be made available to further amplifier stages. This enables a simple interconnection of a plurality of amplifier stages.
In the amplifier, both amplifier paths provide amplification and a signal for operating-point stabilization is derived from both paths, with the result that a fully differential, highly symmetrical amplifier circuit is present. As a result, with a smaller current consumption, a significantly higher gain than in the case of known differential amplifiers is obtained. In addition, it is possible to provide a very small supply voltage of less than 2 volts, as is required in modern CMOS technologies with feature sizes of less than 0.2 micrometer.
In a preferred refinement of the invention, the amplifier paths are driven by half of the operating voltage or supply voltage i.e., the operating point of the transistors of the amplifier paths is put at half of the operating voltage. In this drive range, the slope of the transfer characteristic of a complementary MOSFET is maximal and a correspondingly high gain is made available. A further advantage that results is that a plurality of differential amplifiers can be connected in series in a simple manner.
However, an asymmetrical design also lies within the scope of the invention, in which case, the driving is effected by a voltage shifted from half of the operating voltage. The transistors must then be dimensioned accordingly.
Preferably, the operating point of the two amplifier paths is set by setting the gate voltage of at least two FET control transistors that control the current supply for the two amplifier paths. The gate terminal of the FET control transistors in each case are coupled to the node between the two load resistors. In particular, the FET control transistors are a CMOS pair with a p-channel control transistor and an n-channel control transistor.
The voltage at the node between the load resistors controls the gate voltage, and therefore the current supply for the CMOS control transistors. The operating point for the first and second amplifier paths is set by way of the current supply. In this case, the control transistors for the amplifier paths act as operating-point-stabilizing resistors.
In a preferred design of the invention, the source terminal of the p-channel control transistor is connected to the operating voltage and the source terminal of the n-channel control transistor is connected to ground and the first and second amplifier paths are arranged between the drain terminals of the two control transistors. For this purpose, the drain terminal of the p-channel control transistor is connected to the source terminal of the p-channel transistor of the first amplifier path and to the source terminal of the p-channel transistor of the second amplifier path, and the drain terminal of the n-channel control transistor is connected to the source terminal of the n-channel transistor of the first amplifier path and to the source terminal of the n-channel transistor of the second amplifier path. The respective p-channel and n-channel transistors have corresponding operating parameters, with the result that a fully symmetrical circuit is present.
The FET control transistors are preferably operated in the triode region. In this case, they act as resistors having a linear behavior. As a result, the feeding of current into the amplifier paths can be set by way of the operating voltage.
In an advantageous development of the invention, the node between the two load resistors of the amplifier paths that operate relative to one another is coupled to a capacitor. This has the advantage that any asymmetries at the node which might influence the control transistors are filtered out.
In a further development of the invention, the node between the two load resistors is connected via a respective low-pass filter to the gate terminals of the control transistors. As a result, any asymmetries at the node are likewise filtered out, so that no AC signals are present at the control transistors.
In a preferred refinement of the amplifier, the control transistors are in each case assigned a current mirror circuit with a MOSFET transistor having an input that is likewise connected to the node between the two load resistors. As a result, the control transistors can be operated in saturation. As a consequence, the amplifier paths acquire a greater resistance and the gain increases.
The first and second amplifier paths advantageously have additional a negative feedback device which stabilizes the circuit. The negative feedback device preferably has resistors, which are in each case connected to the source terminals of the first and second amplifier paths. By using the resistors, it is possible to widen the bandwidth of the amplifier (at the expense of the gain), i.e. a gain decrease commences only at higher frequencies.
The resistors are advantageously arranged such that the control transistors are, in each case, divided into two transistors of identical size having gate terminals connected to the node between the load resistors, source terminals connected to the operating voltage and ground, respectively, and drain terminals connected to one of the two amplifier paths. Two parallel paths of amplifier paths and control transistors are produced. The two paths are connected to one another (between an amplifier path and a control transistor) in each case by at least one resistor.
In this case, advantageously, a respective capacitor is connected in parallel with the resistors. By additionally increasing the high-frequency signal components, the resulting RC elements accelerate the rise edges of a digital signal to be amplified (so-called xe2x80x9cpeakingxe2x80x9d).
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a differential, complementary amplifier, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.